GigaChip Alliance
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GigaChip® Interface

The GigaChip® Interface is a reliable serial chip-to-chip transport protocol that operates over Optical Internetworking Forum (OIF) standard CEI SerDes and achieves 90% efficiency. The protocol, called the GigaChip Interface (GCI), can be scaled to 1, 2, 4 or 8 SerDes lanes as well as multiples of 8s. It targets computational and memory solutions with serial interfaces for networking equipment such as MoSys’ Bandwidth Engine® family of ICs. Operating on existing devices with 16 lanes at 15 Gbps, GCI provides enough bandwidth to support 4.5B read/write transactions and sufficient bandwidth to buffer full duplex 200GE. Doubling the pins or doubling the line rate (30Gbps) achieves full duplex 400GE.

The GigaChip Interface is groundbreaking technology that has been developed specifically for serial chip-to-chip communications targeting high-speed networking applications. Founded in July 2010 by MoSys, Inc., GigaChip Interface promoters include leading companies Altera Corporation, LSI Corporation , MoSys, Inc., and Xilinx, Inc.