GigaChip Alliance
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GigaChip® Interface

The GigaChip Interface is high efficiency short-reach, low-power serial interface, intended for chip to chip communication in the enterprise and carrier class markets. By closely defining the scope and optimizing for memory type transactions GCI delivers the highest transport efficiency at the lowest protocol latency of any serial interface standard. This enables highly efficient, high-bandwidth, low-latency performance not achievable using currently other serial protocols. The payload granularity of 72 bit, with the CRC and error auto-recovery mechanism ensures the reliability of data transmission. Similar to the fundamental performance breakthrough achieved by the move to double data rate (DDR) style interfaces in the late '90s, the GigaChip Interface represents the next breakthrough in chip-to-chip communications using differential SerDes technology.


A 16-lane GigaChip Interface can replace up to six separate DDR4 parallel interface busses to memory, which represents a bandwidth density performance increase of 4 times, while reducing system power and interface costs by 2 to 3 times. Such bandwidth density increases will be required to realize line cards with aggregate throughput beyond 200G, a necessity in future high end networking systems.


The GigaChip Interface has adopted the open CEI-11 electrical transport standard making use of this existing electrical ecosystem in order to shorten time to market for the introduction of next generation system designs. Through the GigaChip Alliance, companies are enabling an entirely new class of low-cost, high-speed, high-performance systems in networking, computing and storage markets.


GigaChip Interface Spec

Click here to download the GigaChip Interface specification document.
Watch the demo

Going Serial: Breaking the Billion Accesses per Second Barrier
The GigaChip Interface: Efficient, Board-Level Chip-to-Chip Look-Aside Communication